Stories
Slash Boxes
Comments

News for nerds, stuff that matters

Slashdot Log In

Log In

Create Account  |  Retrieve Password

The Truth About Last Year's Xbox 360 Recall

Posted by kdawson on Tue Jun 10, 2008 07:03 PM
from the value-for-the-money dept.
chrplace forwards an article in which Gartner's Brian Lewis offers his perspective on what led to last year's Xbox 360 recall. Lewis says it happened because Microsoft wanted to avoid an ASIC vendor. "Microsoft designed the graphic chip on its own, cut a traditional ASIC vendor out of the process, and went straight to Taiwan Semiconductor Manufacturing Co. Ltd., he explained. But in the end, by going cheap — hoping to save tens of millions of dollars in ASIC design costs, Microsoft ended up paying more than $1 billion for its Xbox 360 recall. To fix the problem, Microsoft went back to an unnamed ASIC vendor based in the United States and redesigned the chip, Lewis added. (Based on a previous report, the ASIC vendor is most likely the former ATI Technologies, now part of AMD.)"
+ -
story

Related Stories

This discussion has been archived. No new comments can be posted.
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
 Full
 Abbreviated
 Hidden
More
Loading... please wait.
  • by ZiakII (829432) <halfwarr@gmail.cNETBSDom minus bsd> on Tuesday June 10 2008, @07:06PM (#23737903)
    Microsoft designed their own graphic chip and it crashed? I'm shocked... I tell you shocked!
  • by Udo Schmitz (738216) on Tuesday June 10 2008, @07:09PM (#23737953) Journal
    Shaking fists at ATI, yelling: "I'll design my own chip! With blackjack! And hookers! ... In fact ..."
  • by Naughty Bob (1004174) * on Tuesday June 10 2008, @07:10PM (#23737961)
    I know /. does like to stick the boot into MSFT whenever possible, but in the last 2 hours there has been 3 front page stories, real stories, about the nasty behaviour of MSFT coming back to bite them in their fugly corporate ass.

    Or is it all just a hoax? [fugue.com]

    Hope not.
  • Another Talisman CF (Score:5, Interesting)

    by rimcrazy (146022) on Tuesday June 10 2008, @07:11PM (#23737965)
    I had the miss-pleasure of working on a graphics ASIC with MicroSquish back around the late 90's on a project called Talisman.

    Never, and I say NEVER let a bunch of software engineers try to design a hardware chip. This was the biggest CF I'd seen in all my years (30+) as a chip designer. That they did it again, and with such stupidity again is no friggin surprise.

    It is not that software engineers should not be involved, of course they should but when they drive the architecture in complete void of any practical chip design constraints..... and continually refuse to listen to any reason from the hardware designers..... well as they say, garbage in, garbage out.
    • by Dhar (19056) on Tuesday June 10 2008, @07:31PM (#23738257) Homepage

      Never, and I say NEVER let a bunch of software engineers try to design a hardware chip.
      I've worked with software written by a hardware company, and I can say the same thing from my side of the fence...never let a bunch of hardware guys write software!

      I suppose if we can all agree to stay out of the other guy's yard, we can get along. You do hardware, I'll do software. :)

      -g.
      • by hedronist (233240) * on Tuesday June 10 2008, @08:26PM (#23739165)
        > never let a bunch of hardware guys write software

        I testify, Brother, I TESTIFY!

        30 Years ago, I ended up in therapy (literally) after dealing with an assembly program written by a hardware guy. The program emulated a CDC communications protocol that was originally done in hardware. This was on a Cincinnati Milacron 2200B, a machine that had both variable instruction length and variable data length. The hardware guy had implemented the protocol state changes by putting a label *on the address portion* of jump statements (he did this in 50 different places in the program) and then in some other area of the code he would change where the jump branched to next time through. It bordered on an implementation of the mythical COME FROM instruction. Of course, there was zero documentation and almost zero comments.

        After one marathon debugging session I was so frustrated I was in tears. My manager came in and wanted to know what the problem was. I gave him the listing and left to walk around the building a few times. When I came back, he told me that it was, hands down, the worst piece of crap he had seen in 20 years. He had me rewrite it from scratch, which I did over a long weekend.

        The program's name was RIP/TIP (Receive Interrupt Processor/Transmit Interrupt Processor) and I was in therapy for most of a year. (There were a few other issues, but this was the bale of hay that made me snap.)

      • by Cassini2 (956052) on Tuesday June 10 2008, @08:12PM (#23738879)

        I am a person that designs both hardware, and software, but not chips, At the risk of talking outside of my expertise, I will have a go at answering your question.

        Firstly, there are things that software people really like, but it is often better to not do them in hardware. This category contains things like Read/Write I/O registers. From a software point of view, they are nice, but they can double your gate count. They can also increase your capacitive bus loading. DAC and ADC designs can also be affected this way. A software person might use a proper ADC and expect proper ADC registered results. A hardware person might select a resistor, capacitor, a voltage comparitor, and a couple of spare I/O pins. The cheesy R/C approach may save the hardware design from a whole slew of problems including cost. A software person may opt for a synchronous logic approach with all registers clocked every clock cycle. The hardware designer may opt for a much more asynchronous approach, that minimizes the number of clocked registers. This reduces power consumption, and potentially the number of registers too. Often the hardware designer will consider thermal, cost, electrical layout issues as part of his design process. The software person will not be as familiar with how to design a good circuit board and chip design in a cost-effective manner. A good software engineer can learn all of this material with time, but the hardware engineers will do them naturally.

        The second category of problems is tools. The modern chip designer is working with a fairly advanced set of tools that the software person is likely to be quite unfamiliar with. This starts with the IC design tools, which are quite specialized. It ends with the hardware engineering tools. Have you ever X-Rayed a circuit board to analyze the cracks in the Ball Grid Array where it bonds to the circuit board? Are you familiar with thermal issues, and thermal images? How about EMI test results? Modern IC package design limitations? A good team of engineers will be familiar with these tools, and know how to use them to get good results.

        The third category of problems is mistakes from inexperience, or lack of experience in the correct field. I work with industrial electronics. I think from an industrial point of view. What happens when someone attaches 600 (VAC) to the ground wire of the computer? What happens to the remote sensors when the plant gets hit by lightening? In IC design, there are some known gray areas too. Does the chip reset properly on power up? Do metastable, astable, or self-oscillating states exist in the IC design? Can the chip survive with no cooling? Does the chip have an overtemp shutdown function? What happens if someone starts the chip up in sub-zero weather? Do the analog electronics have sufficient electrical separation from the digital electronics, while avoiding nasty things like ESD latchup conditions?

        I've completed chip design courses before, but have never had to design a modern production gate array design. As a person that has done both software and hardware, I know that my skills are not good enough for the most modern IC design processes. My limit is FPGA work, and my preference is clever opto-isolation, power semiconductor, TTL and micro-proccessor based circuits. In analog, my expertise in analog is industrial sensing and survivability. You have to know where your field of expertise is, and what your limits are.

          • by CastrTroy (595695) on Tuesday June 10 2008, @09:09PM (#23739871) Homepage
            Not really. I wouldn't have a mechanical engineer design a chip either. I also wouldn't have a hardware/mechanical engineer designing a software system. Let people do what they are good at, and stop trying to cut corners by substituting in people where they have no skills.
  • Ridiculous (Score:5, Informative)

    by smackenzie (912024) on Tuesday June 10 2008, @07:17PM (#23738079)
    ATI and Microsoft developed this chip together over a period of two years. The XBOX 360 GPU has been known since conception as an ATI GPU.

    Furthermore, the recall was for overheating in general which -- though unquestionably affected by the GPU -- is a more comprehensive system design failure, not just a single component. (Look at the stability success they have had simply by reducing the size of the CPU.)

    I'm looking forward to "Jasper", the code name for the next XBOX 360 mother board that will include a 65 nanometer graphics chip, smaller memory chips and HOPEFULLY a price reduction.
    • Vote parent up (Score:5, Insightful)

      by imsabbel (611519) on Tuesday June 10 2008, @07:39PM (#23738351)
      The article is COMPLETE, UTTER bullshit.

      Years before the xbox360 has been released ATI was already announced as the system parter for the GPU. No "secret unnamed ASIC vendor" anywhere.
      The recall, again, was thermal problems.

      Do you really think a completely different GPU by a completely different company could have been designed in a year _and_ totally compatible with the original one?
  • What's going on..... (Score:5, Informative)

    by ryszards (451448) * on Tuesday June 10 2008, @07:25PM (#23738161) Homepage
    Microsoft didn't design the GPU, ATI did, and everyone knows ATI have always been fabless. TSMC are the manufacturer of the larger of the two dice that make up the Xenos/C1 design, and while that die has been revised since for a process node change, it doesn't even appear if that new revision has been used yet (despite it being finished by ATI a long time ago).

    Lewis seems to be just plain wrong, which is kind of upsetting for "chief researcher" at a firm like Gartner, especially when the correct information is freely available.

    While the cooling solution for the GPU is the likely cause of most of the failures, that's not necessarily the GPU's fault, or ATI's, especially for a fault so widespread.
      • by afidel (530433) on Tuesday June 10 2008, @08:06PM (#23738757)
        Now scaler chip makes a LOT more sense to me than the GPU. Everyone knows ATI was the partner for the GPU and there would be few people in the industry that would call a GPU an ASIC. A scaler chip is very much an ASIC and I can see where MS might decide to do their own scaler chip, but they had no chance of doing their own modern GPU without a partner.
  • by YesIAmAScript (886271) on Tuesday June 10 2008, @07:56PM (#23738591)
    Look at Bunnie Huang's analysis.

    The problem wasn't any chip at all. It wasn't even heat. The problem was the chips were not soldered to the board.

    http://www.bunniestudios.com/blog/?p=223 [bunniestudios.com]

    Doesn't matter who designed or made the chips. If they aren't soldered down, they won't work. And that's what the problem was. That's why X-clamps (mostly) work.

    Heat is semi-tangential. If the chip is soldered down, heat won't pop it off and if it isn't soldered, any kind of movement will break it loose, even when cold. This is how MS could ship you replacement units that were RRoD out of the box. They were fine before they were shipped and were broken loose during shipping.

    Most of the problem appears to be solderability problems, not a problem with chip design or manufacturing.
    • by boner (27505) on Tuesday June 10 2008, @07:13PM (#23738003)
      well, it's the difference between an MBA making a business call based on cost/profit analysis and an experienced chip designer looking at the actual risks involved....

      MBAs are good in cutting corners in traditional businesses, but generally have no understanding of technology risks....
      • by CyberLife (63954) on Tuesday June 10 2008, @08:11PM (#23738853)

        MBAs are good in cutting corners in traditional businesses, but generally have no understanding of technology risks....
        This sort of arrogance is so common it's not even funny. I once presented a GIS plot to such a person. You know, the kind of thing that crunches so much data it takes a cluster of machines upwards of several minutes just to produce a single frame? Well this guy argued if I needed so much computer power to make a simple picture I must be doing something wrong.
        • by Anonymous Coward on Tuesday June 10 2008, @08:58PM (#23739683)

          So if you have business savvy you can't possibly understand technology risks? Oh please.
          Strawman. The problem is that MBA degrees are churned out as "one size fits all" managers, suitable (pun intended) for any industry by virtue of having no specific training for any of them.

          You can have business savvy and technological expertise, but it's a roundabout path through today's educational system if you're not teaching yourself at least one. And I think we all know the proportion of people who are capable of serious self-education.

    • by HiVizDiver (640486) on Tuesday June 10 2008, @08:32PM (#23739263)
      Not so sure about that... I would argue that very often when something breaks, it is because they used a cheap vendor, but that the logic doesn't necessarily apply backwards - that using a cheap vendor means it WILL break. I bet there are loads of examples of people doing things on the cheap, where it DIDN'T fail. You just don't hear about those.